The present invention relates to a semiconductor integrated circuit, and more specifically to an electrostatic discharge protection circuit that protects an internal circuit from damage due to electrostatic discharge (ESD).
Electrostaticity is one of the important factors that have an effect on reliability of a semiconductor integrated circuit. Electrostaticity can be charged in a human body and/or a machine. When the human body and/or a machine charged with electrostaticity contacts a semiconductor integrated circuit, the electrostaticity is discharged to the internal circuit via an input/output pad through an external pin of the semiconductor integrated circuit to damage the internal circuit. Therefore, most semiconductor integrated circuits include an electrostatic discharge protective circuit between the input/output pad and the internal circuit in order to protect the internal circuit from damage resulting from the electrostatic discharge.
Referring to FIG. 1, a conventional electrostatic discharge protective circuit includes transfer units 106 and 108 for every input/output pad 100, a trigger unit 110, a discharge unit 120, and a clamp unit 130 to protect a circuit (for example, an input buffer 140) from the damage of electrostatic discharge.
When a positive potential electrostatic current is generated at an input/output pad 100 from a ground voltage terminal 104, the transfer unit 106 induces electrostatic current to a power supply voltage bus line VDD_BL through a diode D1.
When a drain voltage of an NMOS transistor N1 is raised due to the electrostatic current induced to the power supply voltage bus line VDD_BL and exceeds an electrostatic discharge triggering voltage (ESD triggering voltage), the discharge unit 120 discharges the electrostatic current induced to the power supply voltage bus line VDD_BL to the ground voltage terminal 104 through a drain-substrate-source of the NMOS transistor N1.
At this time, the electrostatic discharge triggering voltage of the NMOS transistor N1 depends on the size of the NMOS transistor N1 and the gate voltage. The higher the gate voltage and the larger the size of the NMOS transistor N1, the lower the electrostatic discharge triggering voltage becomes, making it possible to rapidly discharge the electrostaticity.
Accordingly, the trigger unit 110 induces the gate voltage of the NMOS transistor N1 so that the discharge unit 120 is turned-on at low voltage. Specifically, the trigger unit 110 responds to a rapid signaling rising time characteristic of the electrostatic current so that alternating current induced to the power supply voltage bus line VDD_BL flows to a resistor R1 through a capacitor C1 to generate a voltage drop across the resistor R1. The voltage drop allows the same voltage as the power supply voltage bus VDD_BL to be applied to a gate of the NMOS transistor N1 by an inverter IV1. As a result, the electrostatic discharge triggering voltage of the NMOS transistor N1 is lowered, making it possible to more rapidly discharge the electrostaticity.
Meanwhile, the clamp unit 130 discharges the electrostatic current applied to an input buffer 140 to the ground voltage bus line VSS_BL so that the input buffer 140 can be protected from the electrostatic current.
However, the representative conventional electrostatic discharge protective circuit shown in FIG. 1 includes the trigger unit 110 for every input/output pad 100 in addition to the discharge unit 120 that is a direct path of the electrostatic discharge, thereby increasing an area occupied by the electrostatic discharge protective circuit.
Also, as semiconductor technology develops, gate-insulating films of MOS transistors P1 and N2, constituting the input buffer 140, are becoming thinner. In this situation, when the gate insulating films′ breakdown voltage of the MOS transistors P1 and N2 constituting the input buffer 140 is lower than the electrostatic operating voltage of the clamp unit 130, there is a problem in that the gate insulating film may break down before the clamp unit 130 performs the discharge operation.
Recently, U.S. Pat. No. 6,724,603 suggested an electrostatic discharge protective circuit including one trigger unit for every plurality of input/output pads in order to reduce the area of the electrostatic discharge protective circuit as seen in FIG. 2.
Referring to FIG. 2, another conventional electrostatic discharge protective circuit includes transfer units 206, 208, 209, discharge units 220, and one trigger unit 210 for every plurality of input/output pads 200. The trigger unit sends triggering signals to the plurality of discharge units 220 through a trigger bus line TRG_BL.
When a positive potential electrostatic signal is generated at least one input/output pad 200 corresponding to a ground voltage terminal 204, the transfer unit 206 induces electrostatic current to a power supply voltage bus line VDD_BL and at the same time, the transfer unit 209 induces the electrostatic current to a boost bus line BST_BL.
The trigger unit 210 responds to the alternating current of the electrostaticity flowed into the boost bus line BST_BL, forms a current path between the boost bus line BST_BL and the ground power supply bus line VSS_BL, and applies the output trigger voltage from the current path to the plurality of discharge units 220 through the trigger bus line TRG_BL.
At least one discharge unit 220 is triggered according to a state of the trigger bus line TRG_BL, thereby discharging the electrostatic current induced to the power supply voltage bus line VDD_BL to the ground voltage terminal 204.
As such, the conventional electrostatic discharge protective circuit of FIG. 2 includes one trigger unit for every plurality of input/output pads making it possible to greatly reduce a required area for the electrostatic discharge protective circuit within the semiconductor integrated circuit as compared to the conventional electrostatic discharge protective circuit of FIG. 1 including a trigger unit for every input/output pad.
However, the conventional electrostatic discharge protective circuit of FIG. 2 still suffers from weak protection of the input buffer from the electrostaticity generated from the input/output pad like that of the conventional electrostatic discharge protective circuit of FIG. 1.